1. Field of the Invention
The present invention relates generally to a read-only memory and specifically to an EEPROM type programmable read only memory having a variable read voltage.
2. Description of the Related Art
In the case of programmable read-only memories of the EEPROM type, a memory cell is constructed using two MOS transistors and arranged at the crossover point between a word line WL and a bit line BL. This is illustrated in FIG. 3. One of the transistors ST has an insulated gate electrode FG, the charge state of which can be used to set the threshold voltage of this transistor. This transistor ST is the actual memory transistor. In the case of an erased memory cell having n-channel transistors, the insulated gate electrode is negatively charged, with the result that the threshold voltage of the memory transistor ST is shifted towards higher values. In the case of a programmed memory cell, the insulated gate electrode is discharged or even positively charged. The threshold voltage then corresponds to that of a customary MOS transistor or is lower. For the purpose of reading, a read voltage U.sub.L, which lies approximately between the threshold voltages of a programmed and an erased memory transistor, is applied to the control gate electrode SG of the memory transistor ST. If the transistor is erased, it is in the off state; if it is programmed, it will turn on. In the case of p-channel transistors, the conditions are exactly the opposite.
A selection transistor AT, whose drain electrode is connected to a bit line BL and whose gate electrode is connected to a word line WL, is connected in series with this memory transistor ST. By applying a voltage corresponding approximately to the supply voltage V.sub.DD to the word line WL or the gate of the selection transistor AT, the latter is turned on and connects the drain terminal of the memory transistor ST to the bit line BL. The latter is charged to approximately the supply voltage potential V.sub.DD prior to a reading operation. If the cell is erased, the memory transistor ST is in the off state and the bit line BL remains at the supply voltage potential V.sub.DD. A logic "1" is read out. If the cell is programmed, the memory transistor ST is in the on state and the bit line BL is discharged via it, with the result that a logic "0" can be detected after a certain amount of time. These facts are illustrated in the upper part of FIG. 4. At an instant t0, the bit line BL is charged to a voltage U.sub.BL having a value of approximately V.sub.DD. At the instant t1, the voltage U.sub.WL on the word line WL is switched to a value of approximately V.sub.DD by, for example, the falling edge of a clock signal clock1. In the case of an erased cell, which is represented by a I, the voltage U.sub.BL of the bit line remains at the value V.sub.DD, whereas in the case of a programmed cell, which is represented by a II, the voltage U.sub.BL of the bit line decreases.
If the frequency of the clock signal clock1 is small enough, an evaluation operation can be triggered at the instant t2 by the next falling edge. At this instant, the bit line BL has already been discharged to an extent which is sufficient to be able unambiguously to detect a programmed state.
If, however, it is intended to reduce the access time, the clock frequency must be increased. A doubled clock frequency clock2 is illustrated as an example in FIG. 4. In that case, following connection of the supply voltage V.sub.DD to the word line WL at the instant t1, evaluation would take place after a period at the instant t3. At this instant, however, the bit line BL has not yet been completely discharged in the case of a programmed cell, with the result that there is the risk of incorrect detection.